Heretofore, a communication apparatus has the following problem in digital modulation if an analog signal line and an asynchronous digital signal line are arranged close to each other in the communication apparatus. More specifically, such close arrangement allows toggles in the digital signal to interfere with the analog signal, and thereby sharp peaks sometimes appear in the analog signal. When the analog signal thus influenced by the interference is sampled, the peaks are also taken into the samples. Consequently, the resultant data includes large noise and communication quality deteriorates. To address this problem, one possible way is to take such a measure in the layout process as to avoid signal line arrangement in which digital and analog signal lines are arranged close to each other, for example. However, an increase in the integration degree makes it difficult to take this measure in the layout process. Instead, another possible way is to take a measure using error correction code. However, when the error correction code is used to correct a signal influenced by the interference, the exerted error correction performance is lower than the intrinsic performance level of the error correction code. For this reason, as a method of reducing interference with an analog signal from a digital signal, there is a technique of reducing influence of interference by interpolation processing using a digital filter. This interference reduction technique is disclosed in Japanese Patent Application Publication No. Hei 06-252973. Also there is a technique of reducing influence of interference by performing sampling at timings shifted from originally-designed timings. This interference reduction technique is disclosed in Japanese Patent Application Publications Nos. Hei 09-153802 and 2001-53609.
However, these techniques have a drawback in that the techniques can produce the effects by only when a digital signal of interference origin and sampling clock are synchronous with each other, but cannot obtain good communication quality when the digital signal and the sampling clock are asynchronous with each other.